The invention is generally related to integrated circuit device architecture and design, and in particular to the architecture and design of a memory controller for controlling data transfer with a memory storage device.
Computers and other data processing systems rely extensively on various memories to store information used by such systems in performing computer tasks. A memory may be used, for example, to store a portion of a computer program that is executed by a computer, as well as the data that is operated upon by the computer.
Memories may also be found in many of the components of a computer. For example, a microprocessor, the xe2x80x9cbrainsxe2x80x9d of a computer, may have a dedicated cache memory that permits faster access to certain data or computer instructions than otherwise available from the main memory of the computer. Also, dedicated memory may be used by a graphics controller to store the information to display on a computer monitor or other display.
Memories may also be found in many types of interfaces for a computer, e.g., to interface a computer with other computers via an external network. The interfaces are typically implemented using dedicated hardware, e.g., a network adapter card that plugs into the computer and has the necessary connectors for connecting to a particular type of network. A controller is typically used to handle the transfer of data between the computer and the network, and a dedicated memory is typically used to store control data used by the controller, as well as a temporary copy of the data being transmitted over the interface.
Memory used in the above applications are typically implemented using one or more solid-state memory storage devices, or xe2x80x9cchipsxe2x80x9d. A dedicated memory controller is typically used to handle the data transfer to and from such memory storage devices according to a predefined protocol.
Memory storage devices typically have one or more timing characteristics that define the minimum delays that one must wait before performing certain operations with the devices. Timing parameters, related to such characteristics, are thus defined for specific memory storage device implementations. These timing parameters are often limited by the physical structures of the devices, and are defined by the designers of the devices to ensure reliable operation of the devices. As but one example, one type of memory storage device, a dynamic random access memory (DRAM) device, requires that circuitry within the device be xe2x80x9cprechargedxe2x80x9d for at least a predetermined time before data can be read from the device. Should the timing parameter associated with this characteristic for a specific memory storage device implementation not be met, errors may occur in the device, which could jeopardize the validity of the data.
Different types of memory storage devices may have different timing parameters. Moreover, as technology improves, memory storage devices of a given type may be improved over past designs, and as a result may have different timing parameters from the past designs.
To control data transfer with a given type of memory storage device, a memory controller must often be specifically tailored to meet the various timing parameters for that device. To ensure the best possible performance with a given type of memory storage device, it is often desirable for the memory controller to set the delays between various memory control operations to meet or only slightly exceed the timing parameters defined for the device.
Some memory controllers, however, may need to be used with different types of memory storage devices. For example, it may be desirable to support multiple types of memory storage devices so that the memory controller may be used in different applications. However, to support multiple types of memory storage devices often necessitates that a memory controller be designed to handle the worst case timing parameters of a given memory storage device, since the timing parameters typically define minimum acceptable delays. As a result, when a memory controller is used with a memory storage device having timing parameters that offer faster performance than the worst case timing parameters defined for the controller, the memory storage device is operated at below its maximum performance level, and the improved performance that could otherwise be realized by the device is lost.
Some conventional memory controller designs attempt to support different timing parameters for a given timing characteristic by controllably inserting one or more xe2x80x9cwait statesxe2x80x9d into a memory access operation to account for a performance mismatch between the controller and a memory storage device. Typically, such controller designs support one of two timing parameters by controllably selecting one of two possible xe2x80x9cpathsxe2x80x9d of execution.
Specifically, a memory controller typically operates using a state machine that cycles between different xe2x80x9cstagesxe2x80x9d to perform different memory control operations associated with controlling the data transfer with a memory storage device. The state machine is timed by a clock signal that defines the time to wait between each stage. A path of execution is defined by the sequence of stages that are sequentially performed in the state machine when following the path.
An important limitation of such conventional memory controller designs is that supporting a second path of execution can significantly increase the complexity of the state machine, which tends to increase the overall cost and complexity of the controller. Moreover, the complexity of the state machine increases dramatically as the number of execution paths increases. Furthermore, if it is desirable to support variable timing parameters for multiple timing characteristics, the complexity of the state machine increases at an even greater rate. As a result, conventional memory controller designs are typically limited to supporting only a very few timing parameters for only a very few timing characteristics.
Furthermore, due to the inability of conventional memory controller designs to support a wide variety of memory storage devices, it is often not cost-effective to anticipate the use of such designs with future memory storage devices that may have shorter timing parameters, and as a result improved performance, over current devices. Consequently, often new memory controller designs must be developed in response to advances in memory storage device technology.
Therefore, a significant need continues to exist for a more flexible and extensible memory controller design that is capable of supporting a wider variety of memory storage devices.
The invention addresses these and other problems associated with the prior art by providing a memory controller circuit arrangement and method that utilize a tuning circuit that controls the timing of memory control operations via one or more programmable delay counters. Each counter is programmed to cycle a selected number of clock cycles to delay performance of a memory control operation to meet a predetermined timing parameter for a memory storage device coupled to the controller.
A programmable delay counter may be used, for example, to enable a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit, among other implementations. As a result, a single path of execution in the logic circuit may be used to support any number of timing parameter variations for a particular timing characteristic. Moreover, through the use of multiple programmable delay counters, multiple timing characteristics may be adjusted within the same path of execution. Consequently, a wide variety of timing characteristics and timing parameters therefor may be supported in a single integrated design, offering greater flexibility and extensibility than conventional designs.
Therefore, consistent with one aspect of the invention, a memory controller circuit arrangement is provided, including a logic circuit and a tuning circuit. The logic circuit is configured to control data transfer with at least one memory storage device by performing first and second memory control operations. The memory storage device of the type having a predetermined timing parameter that defines a minimum delay between the first and second memory control operations. The tuning circuit is coupled to the logic circuit and is configured to control the delay between the first and second memory control operations to meet the predetermined timing parameter for the memory storage device by cycling a programmable delay counter a selected number of clock cycles to delay performance of the second memory control operation.
These and other advantages and features, which characterize the invention, are set forth in the claims annexed hereto and forming a further part hereof. However, for a better understanding of the invention, and of the advantages and objectives attained through its use, reference should be made to the Drawings, and to the accompanying descriptive matter, in which there is described exemplary embodiments of the invention.